1. Field of the Invention
The present invention relates to a semiconductor memory device and method of operation, and more particularly, to a semiconductor memory device and method of operation wherein memory cells require refreshing of storage data, wherein refreshing operations are performed internally, and wherein the device operates externally with timing requirements similar to those of a static RAM.
2. Description of the Related Art
Random-access memory (RAM) devices store electronic data in an array of individually-addressable elements known as memory cells. Two basic types of RAM cells are prevalent in the marketxe2x80x94the static RAM (SRAM) cell and the dynamic RAM (DRAM) cell. The SRAM cell has a static latching structure (e.g., comprising six transistors, or four transistors and two registers) that can store data indefinitely. The DRAM cell has a storage node (e.g., a capacitor) and a single access transistor. Data is stored in the cell by setting the charge state of the storage node.
Because all capacitors exhibit charge leakage, a characteristic of the DRAM cell is that it cannot hold data indefinitely. A charged storage node will eventually discharge to a point where it will be misread as a discharged storage node, causing a data error. To prevent this from occurring, DRAM cells are periodically xe2x80x9crefreshedxe2x80x9d, i.e., charged cells are recharged. This periodic refreshing must revisit each cell many times per second to prevent data loss.
DRAM refreshing requires a refresh circuit to ensure that each cell is revisited before data loss occurs. Early DRAMs (particularly DRAMs that operate externally with timing requirements similar to those of a static RAM) relied on an external memory controller to perform the necessary refresh circuit function. Today, many DRAMs incorporate a refresh circuit into their internal logic, and thus perform xe2x80x9cinternal refreshingxe2x80x9d. Historically, internal-refresh DRAMs have had different external operating requirements than SRAMs. In particular, prior art internal-refresh DRAMs imposed at least one of two external operating requirements that do not exist with an SRAM: a finite write recovery time that is added to the end of every write cycle, and a maximum write cycle time. As will be explained below, a required write recovery time makes DRAM write access time slower than the normal read access time, and the maximum write cycle time imposes an upper limit on the length of an external write cycle.
Despite its peculiarities, the DRAM has some distinct advantages when compared to the SRAM. Chief among these is sizexe2x80x94the DRAM memory cell is typically an order of magnitude smaller than an SRAM memory cell built with similar process technology. This size difference translates into either a less expensive device, or a device that can store more data for the same memory cost. Thus a DRAM that could replace an SRAM without imposing additional external operating requirements on surrounding circuitry is desirable.
U.S. Pat. No. 4,984,208, entitled xe2x80x9cDynamic Read/Write Memory with Improved Refreshing Operationxe2x80x9d, issued to Kazuhiro Sawada et al. on Jun. 12, 1989, discloses two DRAM circuits, one with a write recovery time requirement, and another with a maximum cycle time requirement.
FIG. 1 illustrates the operation of an internal-refresh DRAM circuit with a write recovery time requirement, as disclosed in the background of the ""208 patent. A write operation is shown in FIG. 1 between times t0 and t3. The write operation is initiated externally by setting up the write address on ADD at time t0, and then taking the write enable signal WE# low. After the data to be written is set up on I/O, write enable signal WE# is taken back high at t1, signaling the DRAM circuit that it may now read the data off of I/O. But in FIG. 1, at time t1 the circuit has just begun a refresh operation by selecting a refresh word line RWL. Thus the start of the array write access must be delayed until the end of the refresh operation at t2. At t2, word line NWL1 is finally asserted and the data on I/O is written. The data and address must remain on the input to the device long enough for the refresh to finish and the array write access to begin.
In FIG. 1, the write recovery time t(WR) is the additional time needed after the rising edge of the WE# pulse before another memory operation can be begun. Whereas an SRAM can complete a write operation upon sensing the rising edge of the WE# pulse, this DRAM cannot. This is because the DRAM cannot pre-select the word line NWL1 before data is available on I/O, in order that refresh operations can occur in the interim. FIG. 1 shows the worst case that must be designed for, where a refresh operation has just begun when WE# goes high.
FIG. 2 illustrates the operation of a second DRAM described in the ""208 patent. In FIG. 2, when WE# goes low, a refresh operation has already begun (RWL is selected). When the refresh operation ends, the word line NWL1, corresponding to the address on ADD, is selected, and remains selected for the duration of the WE# pulse. Thus when the data becomes valid on I/O, it can immediately be written, allowing the write operation to end and another operation to begin when WE# goes back high. Thus the operation in FIG. 2 requires no write recovery time, and appears to have the same timing as an SRAM.
As illustrated in FIG. 3, the operation of the second DRAM poses a potential problem that is not present with an SRAM. Because NWL1 remains selected for the write enable pulse duration t(WP), a refreshing operation cannot begin while WE# is low. Thus it the external circuitry initiates a xe2x80x9clong writexe2x80x9d, i.e., it waits too long to release WE#, this may delay a refreshing operation too long to prevent data corruption.
To prevent data corruption, a DRAM operating according to FIGS. 2 and 3 imposes a maximum write cycle time on external circuitry. In other words, t(WP) may be limited, e.g., from one to ten microseconds in duration for each write cycle. This limits the applications for such a device to those that can both tolerate and ensure compliance with a maximum write cycle time requirement.
It has now been recognized that a need exists for a memory device that uses refresh type memory cells, but operates within the same timing parameters as an SRAM. The preferred embodiments of the present invention accomplish just this, by operating with a zero write recovery time and also with no maximum write cycle time limitation. In these preferred embodiments, a refresh operation and a successful read/write operation can both be performed during an external read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refresh operations can also be performed during the single cycle. Since refreshing can continue during a long external read/write cycle, no limitation on maximum cycle time is necessary with the preferred embodiments.
A method for operating a semiconductor memory device having a refresh-type memory cell array is disclosed. In this method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. Consequently, the method does not require the word lines of the memory cell array to be statically-enabled, during the external write command, in order for the device to respond to that command. This allows refresh operations to proceed as needed during the external write command, no matter how long the external write takes to complete.
In some preferred embodiments, an external write command also triggers a pulsed late write to the memory cell array of the register data associated with the last external write command. This frees the registers so that they can be used to store the write address and data associated with the current external write command. But perhaps more importantly, because the late write is pulsed, with its timing controlled by the device, the write occupies a known time period to access the memory cell arrayxe2x80x94no matter what the length of the external write cycle. Outside of this known time period, refresh operations can be allowed.
A semiconductor memory device having a refresh-type memory cell array is also disclosed. The device comprises a refresh circuit, a data input register, a write address register, write circuitry, read circuitry, and control circuitry. The write circuitry initiates a pulsed write operation during an externally-requested current write operation, in order to write data stored in the data input register to the cell array at an address stored in the write address register. The write circuitry also stores the write address received during the current externally-requested write operation to the write address register, and stores the data received during the current externally-requested write operation to the data input register.
The read circuitry initiates a pulsed read operation during an externally-requested current read operation. The read address for the read operation is compared to the address stored in the write address register. When these two addresses are different, data read from the memory cell array is selected for output. When the two addresses match, however, data from the data input register is selected for output.
The control circuitry generates timing signals for pulsed write operation, pulsed read operation, and pulsed refresh operation. The control circuit also disables refresh operation.requests from the refresh circuit during pulsed write operations and pulsed read operations.